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| ? semiconductor components industries, llc, 2009 may, 2009 ? rev. 4 1 publication order number: ncv7341/d ncv7341 high speed low power can transceiver the ncv7341 can transceiver is the interface between a controller area network (can) protocol controller and the physical bus and may be used in both 12 v and 24 v systems. the transceiver provides differential transmit capability to the bus and differential receive capability to the can controller. due to the wide common ? mode voltage range of the receiver inputs, the ncv7341 is able to reach outstanding levels of electromagnetic susceptibility (ems). similarly, extremely low electromagnetic emission (eme) is achieved by the excellent matching of the output signals. the ncv7341 is a new addition to the on semiconductor can high ? speed transceiver family and offers the following additional features: features ? ideal passive behavior when supply voltage is removed ? separate v io supply for digital interface allowing communication to can controllers and microcontrollers with different supply levels ? fully compatible with the iso 11898 standard ? high speed (up to 1 mb) ? very low electromagnetic emission (eme) ? v split voltage source for stabilizing the recessive bus level if split termination is used (further improvement of eme) ? differential receiver with high common ? mode range for electromagnetic immunity (emi) ? up to 110 nodes can be connected in function of the bus topology ? transmit data (txd) dominant time ? out function ? bus error detection with version ncv7341d20 ? bus pins protected against transients in automotive environments ? bus pins and pin v split short ? circuit proof to battery and ground ? thermally protected ? ncv prefix for automotive and other applications requiring site and change controls ? these are pb ? free devices* typical applications ? automotive ? industrial networks *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com pin assignment (top view) see detailed ordering and shipping information in the package dimensions section on p age 17 of this data sheet. ordering information 8 9 10 11 12 13 14 1 2 3 4 5 6 7 txd gnd rxd en wake canh canl vbat ncv7341 pc20060727.1 v cc v io inh stb v split err
ncv7341 http://onsemi.com 2 table 1. technical characteristics symbol parameter condition max max unit v cc supply voltage for the core circuitry 4.75 5.25 v v io supply voltage for the digital interface 2.8 5.25 v v en dc voltage at pin en ? 0.3 v io + 0.3 v v stb dc voltage at pin stb ? 0.3 v io + 0.3 v v txd dc voltage at pin txd ? 0.3 v io + 0.3 v v rxd dc voltage at pin rxd ? 0.3 v io + 0.3 v v err dc voltage at pin err ? 0.3 v io + 0.3 v v canh dc voltage at pin canh 0 < v cc < 5.25 v; no time limit ? 58 +58 v v canl dc voltage at pin canl 0 < v cc < 5.25 v; no time limit ? 58 +58 v v split dc voltage at pin v split 0 < v cc < 5.25 v; no time limit ? 58 +58 v v o(dif)(bus_dom) differential bus output voltage in dominant state 42.5 < r lt < 60 1.5 3 v cm range input common ? mode range for comparator guaranteed differential receiver threshold and leakage current ? 35 +35 v c load load capacitance on ic outputs 15 pf t pd(rec ? dom) propagation delay txd to rxd see figure 6 90 230 ns t pd(dom ? rec) propagation delay txd to rxd see figure 6 90 245 ns t j junction temperature ? 40 150 c esd hbm esd level, human body model pins canh, canl, v split , wake, v bat other pins ? 4 ? 3 4 3 kv ncv7341 http://onsemi.com 3 block diagram v split digital control block wake ? up filter ncv7341 gnd rxd vcc 1 timer vcc txd driver control thermal shutdown pc20060921.1 por + ?? ?? ?? ?? ?? ? wake en clock vbat inh vio 2 3 4 5 6 7 8 9 10 14 stb err canh canl 11 12 13 vsplit ?active? low power rec rec vcc/2 ?active? 26 k 26 k figure 1. block diagram ncv7341 http://onsemi.com 4 typical application schematics stb rxd txd 4 14 can controller gnd gnd 2 5 1 6 pc20060921.4 en err 8 vcc 5v ? reg 11 13 12 vbat inh vio vcc 3710 100nf 100 nf x f* ncv7341 note (*): value depending on regulator out canh canl v split can bus r lt =60 9 wake 180 k 2.7 k 1k r lt =60 c lt = 4.7 nf 10 nf vbat in 10 nf figure 2. application diagram with a 5v can controller ncv7341 stb rxd txd 4 14 can controller gnd gnd 2 5 1 6 pc20060921.4 en err 8 vcc 11 13 12 vbat inh vio vcc 37 10 9 100 nf 100 nf x f* note (*): value depending on regulator 5v ? reg 3v ? reg x f* out out in canh canl v split can bus r lt =60 wake 180 k 2.7 k 1k r lt =60 c lt = 4.7 nf 10 nf vbat in 10 nf figure 3. application diagram with a 3v can controller ncv7341 http://onsemi.com 5 pin description figure 4. ncv7340 pin assignment 8 9 10 11 12 13 14 1 2 3 4 5 6 7 txd gnd rxd en wake canh canl vbat ncv7341 pc20060727.1 v cc v io inh stb v split err table 2. pin description pin name description 1 txd transmit data input; low level = dominant on the bus; internal pull ? up current 2 gnd ground 3 v cc supply voltage for the core circuitry and the transceiver 4 rxd receive data output; dominant bus => low output 5 v io supply voltage for the can controller interface 6 en enable input; internal pull ? down current 7 inh high voltage output for controlling external voltage regulators 8 err digital output indicating errors and power ? up; active low 9 wake local wake ? up input 10 v bat battery supply connection 11 v split common ? mode stabilization output 12 canl low ? level can bus line (low in dominant) 13 canh high ? level can bus line (high in dominant) 14 stb stand ? by mode control input; internal pull ? down current ncv7341 http://onsemi.com 6 functional description operating modes operation modes of ncv7341 are shown in figures 5 and in table 3. power up receive only mode normal mode standby mode goto sleep mode sleep mode stb = h and en = l stb = h and en = h stb = h and en = l stb = h and en = h stb = l and en = h stb = l and en = h and flags reset stb = l and (en = l or flags set) stb = l and (en = l or flags set) stb = h and en = h stb = h and en = l stb = l and en = l stb = l and en = h and flags reset flags reset and t > t h(min) stb = l and flags set stb = h and en = l and v cc /v io undervoltage flag reset stb = h and en = h and v cc /v io undervoltage flag reset legend ?flags set? : wake ? up or power ? up ?flags reset? : not (wake ? up or power ? up) pc20060921.2 figure 5. operation modes ncv7341 http://onsemi.com 7 table 3. operation modes conditions transceiver behavior pin stb pin en v cc /v io undervoltage flag vbat undervoltage flag power ? up or wakeup flag operating mode pin inh x x set x x sleep floating reset set set standby high reset if in sleep, then no change floating otherwise stand ? by high low low reset reset set stand ? by high reset if in sleep, then no change floating otherwise stand ? by high low high reset reset set stand ? by high reset if in sleep, then no change floating otherwise go ? to ? sleep high high low reset reset x receive ? only high high high reset reset x normal high normal mode in normal mode, the transceiver is able to communicate via the bus lines. the can controller can transmit data to the bus via txd pin and receive data from the bus via pin rxd. the bus lines (canh and canl) are internally biased to v cc /2 via the common ? mode input resistance. pin v split is also providing voltage v cc /2 which can be further used to externally stabilize the common mode voltage of the bus ? see figure 2 and figure 3. pin inh is active (pulled high) so that the external regulators controlled by inh pin are switched on. receive ? only mode in receive ? only mode, the can transmitter is disabled. the can controller can still receive data from the bus via rxd pin as the receiver part remains active. equally to normal mode, the bus lines (canh and canl) are internally biased to v cc /2 and pin v split is providing voltage v cc /2. pin inh is also active (pulled high). standby mode standby mode is a low ? power mode. both the transmitter and the receiver are disabled and a very low ? power differential receiver monitors the can bus activity. bus lines are biased internally to ground via the common mode input resistance and pin v split is high ? impedant (floating). a wake ? up event can be detected either on the can bus or on the wake pin. a valid wake ? up is signaled on pins err and rxd. pin inh remains active (pulled high) so that the external regulators controlled by inh pin are switched on. go ? to ? sleep mode go ? to ? sleep mode is an intermediate state used to put the transceiver into sleep mode in a controlled way. go ? to ? sleep mode is entered when the can controller puts pin en to high and stb pin to low. if the logical state of pins en and stb is kept unchanged for minimum period of t h(min) and neither a wake ? up nor a power ? up event occur during this time, the transceiver enters sleep mode. while in go ? to ? sleep mode, the transceiver behaves identically to stand ? by mode. sleep mode sleep mode is a low ? power mode in which the consumption is further reduced compared to stand ? by mode. sleep mode can be entered via go ? to ? sleep mode or in case an undervoltage on either v cc or v io occurs for longer than the under ? voltage detection time. the transceiver behaves identically to standby mode, but the inh pin is deactivated (left floating) and the external regulators controlled by inh pin are switched off. in this way, the v bat consumption is reduced to a minimum. the device will leave sleep mode either by a wake ? up event (in case of a can bus wake ? up or via pin w ake) or by putting pin stb high (as long as an under ? voltage on v cc or v io is not detected). internal flags the transceiver keeps several internal flags reflecting conditions and events encountered during its operation. some flags influence the operation mode of the transceiver (see figure 5 and t able 3). beside the undervoltage and the txd dominant timeout flags, all others can be read by the can controller on pin err . pin err signals internal flags depending on the operation mode of the transceiver. an overview of the flags and their visibility on pin err is given in table 4. because the err pin uses negative logic, it will be pulled low if the signaled flag is set and will be pulled high if the signaled flag is reset. ncv7341 http://onsemi.com 8 table 4. internal flags and their visibility internal flag set condition reset condition visibility on pin err v cc /v io undervoltage v cc < v cc(sleep) longer than t uv(vcc) or v io < v io(sleep) longer than t uv(vio) at wake ? up or power ? up no v bat undervoltage v bat < v bat(stb) when v bat recovers no powerup v bat rises above vbat (pwup) (v bat connection to the transceiver) when normal mode is entered in receive ? only mode. not going from normal mode wake ? up when remote or local wake ? up is detected at power ? up or when normal mode is entered or when v cc /v io undervoltage flag is set both on err and rxd (both pulled to low). in go ? to ? sleep, standby and sleep mode. local wake ? up when local wake ? up is detected (i.e.via pin wake) at power ? up or when leaving normal mode in normal mode before 4 consecutive dominant symbols are sent. then err pin becomes high again failure pin txd clamped low or overtemperature when entering normal mode or when rxd is low while txd is high (provided all failures disappeared) overtemperature condition observable in receive ? only mode entered from normal mode bus failure (ncv7341d20) one of the bus lines shorted to ground or supply during four consecutive transmitted dominants no bus line short (to ground or supply) detected during four consecutive dominant bit transmissions in normal mode v cc /v io undervoltage flag the v cc /v io undervoltage flag is set if v cc supply drops below v cc(sleep) level for longer than t uv(vcc) or v io supply drops below v io(sleep) level for longer than t uv(vio) . if the flag is set, the transceiver enters sleep mode. after a waiting time identical to the undervoltage detection times t uv(vcc) and t uv(vio) , respectively, the flag can be reset either by a valid wake ? up request or when the powerup flag is set. during this waiting time, the wakeup detection is blocked. vbat under ? voltage flag the flag is set when v bat supply drops below v bat(stb) level. the transceiver will enter the standby mode. the flag is reset when v bat supply recovers. the transceiver then enters the mode defined by inputs stb and en. power ? up flag this flag is set when v bat supply recovers after being below v bat(pwup) level, which corresponds to a connection of the transceiver to the battery. the v cc /v io undervoltage flag is cleared so that the transceiver cannot enter the go ? to ? sleep mode, ensuring that inh pin is high and the external voltage regulators are activated at the battery connection. in receive ? only mode, the powerup flag can be observed on the err pin. the flag is reset when normal mode is entered. wake ? up flag this flag is set when the transceiver detects a valid wake ? up request via the bus or via the wake pin. setting the wake ? up flag is blocked during the waiting time of the v cc /v io undervoltage flag. the wake ? up flag is immediately propagated to pins err and rxd ? provided that supplies v cc and v io are available. the wake ? up flag is reset at power ? up or when v cc /v io undervoltage occurs or when normal mode is entered. local wake ? up flag this flag is set when a valid wake ? up request through wake pin occurs. it can be observed on the err pin in normal mode. it can only be set when the powerup flag is reset. the local wake ? up flag is reset at powerup or at leaving normal mode. failure flag the failure flag is set in one of the following situations: ? txd pin is low (i.e. dominant is requested by the can controller) for longer than t dom(txd ) ? under this condition, the transmitter is disabled so that a bus lockup is avoided in case of an application failure which would drive permanent dominant on the bus. the transmitter remains disabled until the failure flag is reset. ? overtemperature ? if the junction temperature reaches t j(sd) , the transmitter is disabled in order to protect it from overheating and the failure flag is set. the transmitter remains disabled until the failure flag is reset. the failure flag is reset when normal mode is entered or when txd pin is high while rxd pin is low. in case of overtemperature, the failure flag is observable on pin err . bus failure flag (ncv7341d20) the transmitter of the ncv7341d20 device version allows bus failure detection. during dominant bit transmission, a short of the canh or canl line to ground or supply (v cc , vbat or other) is internally detected. if the short circuit condition lasts for four consecutive dominant ncv7341 http://onsemi.com 9 transmissions, an internal bus failure flag is set and made immediately visible through a low level on the err pin. the transmission and reception circuitry continues to function. when four consecutive dominant transmissions succeed without a bus line short being detected, the internal bus failure flag is reset and err pin is released to high level. split circuit the v split pin is operational only in normal and receive ? only modes. it is floating in standby and sleep modes. the v split can be connected as shown in figure 2 and figure 3 and its purpose is to provide a stabilized dc voltage of v cc /2 to the bus avoiding possible steps in the common ? mode signal, therefore reducing eme. these unwanted steps could be caused by an unpowered node on the network with excessive leakage current from the bus that shifts the recessive voltage from its nominal v cc /2 level. wake ? up the transceiver can detect wake ? up events in stand ? by, go ? to ? sleep and sleep modes. two types of wake ? up events are handled ? remote wake ? up via the can bus or a local wake ? up via the wake pin. a valid remote wake ? up is recognized after two dominant states of the can bus of at least t dom , each of them followed by a recessive state of at least t rec . a local wake ? up is detected after a change of state (high to low, or low to high) on wake pin which is stable for at least t wake . to increase the ems level of the wake pin, an internal current source is connected to it. if the state of the wake pin is stable at least for t wake , the direction of the current source follows (pulldown current for low state, pullup current for high state). it is recommended to connect pin wake either to gnd or vbat if it?s not used in the application. fail safe features fail safe behavior is ensured by the detection functions associated with the internal flags. furthermore, a current ? limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. the pins canh and canl are protected from automotive electrical transients (according to iso 7637; see figure 9). pins txd is pulled high and pins stb and en are pulled low internally should the input become disconnected. pins txd, stb , en and rxd will be floating, preventing reverse supply should the v io supply be removed. ncv7341 http://onsemi.com 10 electrical characteristics definitions all voltages are referenced to gnd (pin 2). positive currents flow into the ic. sinking current means the current is flowing into the pin; sourcing current means the current is flowing out of the pin. absolute maximum ratings stresses above those listed in the following table may cause permanent device failure. exposure to absolute maximum ratings for extended periods may affect device reliability. table 5. absolute maximum ratings symbol parameter conditions min. max. unit v bat supply voltage ? 0.3 58 v v cc supply voltage ? 0.3 +7 v v io supply voltage ? 0.3 +7 v v canh dc voltage at pin canh 0 < v cc < 5.25 v; no time limit ? 58 +58 v v canl dc voltage at pin canl 0 < v cc < 5.25 v; no time limit ? 58 +58 v v canl ? v canh dc voltage between bus pins canh and canl 0 < v cc < 5.25 v; no time limit ? 58 +58 v v split dc voltage at pin vsplit 0 < v cc < 5.25 v; no time limit ? 58 +58 v v inh dc voltage at pin inh ? 0.3 vbat+0.3 v v wake dc voltage at pin wake ? 0.3 58 v v txd dc voltage at pin txd ? 0.3 7 v v rxd dc voltage at pin rxd ? 0.3 v io + 0.3 v v stb dc voltage at pin stb ? 0.3 7 v v en dc voltage at pin en ? 0.3 7 v v err dc voltage at pin err ? 0.3 v io + 0.3 v v tran(canh) transient voltage at pin canh (note 1) ? 300 +300 v v tran(canl) transient voltage at pin canl (note 1) ? 300 +300 v v tran(vsplit) transient voltage at pin vsplit (note 1) ? 300 +300 v v esd(canl/canh/ vsplit, vbat, wake) electrostatic discharge voltage at pins intended to be wired outside of the module (canh, canl, v split , vbat, wake) (note 2) (note 4) ? 4 ? 500 4 500 kv v v esd electrostatic discharge voltage at all other pins (note 2) (note 4) ? 3 ? 500 3 500 kv v latch ? up static latch ? up at all pins (note 3) 120 ma t stg storage temperature ? 50 +150 c t amb ambient temperature ? 50 +125 c t junc maximum junction temperature ? 50 +180 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. applied transient waveforms in accordance with iso 7637 part 3, test pulses 1, 2, 3a, and 3b (see figure 9). 2. standardized human body model electrostatic discharge (esd) pulses in accordance to mil883 method 3015.7. 3. static latch-up immunity: static latch-up protection level when tested according to eia/jesd78. 4. standardized charged device model esd pulses when tested according to eos/esd ds5.3-1993. ncv7341 http://onsemi.com 11 operating conditions operating conditions define the limits for functional operation, parametric characteristics and reliability specification of th e device. functionality of the device is not guaranteed outside the operating conditions. table 6. operating ranges symbol parameter conditions min max unit v bat supply voltage 5.0 50 v v bat_sleep supply voltage in the sleep mode (note 1) 6.0 50 v v cc supply voltage 4.75 5.25 v v io supply voltage 2.8 5.25 v v canh dc voltage at pin canh receiver function guaranteed ? 35 +35 v v canl dc voltage at pin canl receiver function guaranteed ? 35 +35 v v canl ? v canh dc voltage between bus pins canh and canl receiver function guaranteed ? 35 +35 v v split dc voltage at pin v split leakage and current limitation are guaranteed ? 35 +35 v v inh dc voltage at pin inh ? 0.3 v bat + 0.3 v v wake dc voltage at pin wake ? 0.3 v bat + 0.3 v v txd dc voltage at pin txd ? 0.3 v io + 0.3 v v rxd dc voltage at pin rxd ? 0.3 v io + 0.3 v v stb dc voltage at pin stb ? 0.3 v io + 0.3 v v en dc voltage at pin en ? 0.3 v io + 0.3 v v err dc voltage at pin err ? 0.3 v io + 0.3 v c load capacitive load on digital outputs (pins rxd and err ) 15 pf t a ambient temperature ? 40 +125 c t j maximum junction temperature ? 40 +150 c 1. in the sleep mode, all relevant parameters are guaranteed only for v bat > 6 v. for v bat between 5 v and 6 v, no power ? on ? reset will occur and the functionality is also guaranteed, but some parameters might get slightly out of the specification ? e.g. the wakeup detection thresholds. table 7. thermal characteristics symbol parameter conditions value unit r th(vj ? a) thermal resistance from junction ? to ? ambient in soic ? 14 package 1s0p pcb 128 k/w r th(vj ? a) thermal resistance from junction ? to ? ambient in soic ? 14 package 2s2p pcb 70 k/w ncv7341 http://onsemi.com 12 characteristics the characteristics of the device are valid for operating conditions defined in table 7 and the bus lines are considered to be loaded with r lt = 60 , unless specified otherwise. table 8. dc characteristics symbol parameter conditions min typ max unit supply (pin vbat) vbat (stb) level for setting v bat undervoltage flag v cc = 5 v 2.75 3.3 4.5 v vbat (pwup) level for setting powerup flag v cc = 0 v 2.75 3.3 4.5 v i vbat v bat current consumption in normal and receive ? only modes inh and wake not loaded 1.0 10 40 a v bat current consumption in standby and go ? to ? sleep modes. the total supply current is drawn partially from v bat and partially from v cc . v vcc > 4.75 v, v vio > 2.8 v v inh = v wake = v vbat = 12 v t amb < 100 c 18 a v vcc > 4.75 v, v vio > 2.8 v v inh = v wake = v vbat = 12 v 8.0 12 22.5 a v bat current consumption in sleep mode. the supply current is drawn from v bat only . v vcc = v inh = v vio = 0 v v wake = v vbat = 12 v t amb < 100 c 35 a v vcc = v inh = v vio = 0 v v wake = v vbat = 12 v 10 20 50 a supply (pin v cc ) v cc(sleep) v cc level for setting v cc /v io undervoltage flag v bat = 12 v 2.75 3.3 4.5 v i vcc v cc current consumption in normal or receive ? only mode normal mode: v txd = 0 v, i.e. dominant 25 55 80 ma normal mode: v txd = v io , i.e. recessive (or receive ? only mode) 2.0 6.0 10 ma v cc current consumption in standby and go ? to ? sleep mode. the total supply current is drawn partially from v bat and partially from v cc . t amb < 100 c 17.5 a 6.5 12 19.5 a v cc current consumption in sleep mode t amb < 100 c 1.0 a 0.2 0.5 2.0 a supply (pin v io ) v io(sleep) v io level for setting v cc /v io undervoltage flag 0.9 1.6 2.0 v i vio v io current consumption in normal or receive ? only mode normal mode: v txd = 0v, i.e. dominant 100 350 1000 a normal mode: v txd = v io , i.e. recessive (or receive ? only mode) 0 0.2 1.0 a v io current consumption in standby or sleep mode t amb < 100 c 1.0 a 0 0 5.0 a transmitter data input (pin txd) v ih high ? level input voltage output recessive 0.7v vio ? v io + 0.3 v v il low ? level input voltage output dominant ? 0.3 ? 0.3v vio v i ih high ? level input current v txd = v vio ? 5.0 0 +5.0 a ncv7341 http://onsemi.com 13 table 8. dc characteristics symbol unit max typ min conditions parameter transmitter data input (pin txd) i il low ? level input current v txd = 0.3 v vio ? 70 ? 250 ? 500 a c i input capacitance not tested 1.0 5.0 10 pf standby and enable inputs (pins stb and en) v ih high ? level input voltage 0.7v vio ? v io + 0.3 v v il low ? level input voltage ? 0.3 ? 0.3v vio v i ih high ? level input current v stb = v en = 0.7v vio 1.0 5.0 10 a i il low ? level input current v stb = v en = 0 v ? 0.5 0 5.0 a c i input capacitance 1.0 5.0 10 pf receiver data output (pin rxd) i oh high ? level output current v rxd = v vio ? 0.4 v v vio = v vcc ? 1.0 ? 3.0 ? 6.0 ma i ol low ? level output current v rxd = 0.4 v v txd = 0 v bus is dominant 2.0 5.0 12 ma flag indication output (pin err ) i oh high ? level output current v err = v vio ? 0.4 v v vio = v vcc ? 4.0 ? 20 ? 50 a i ol low ? level output current v err = 0.4 v 100 200 350 a local wake ? up input (pin wake) i ih high ? level input current v wake = v vbat ? 1.9 v ? 1.0 ? 5.0 ? 10 a i il low ? level input current v wake = v vbat ? 3.1 v 1.0 5.0 10 a v threshold threshold of the local wake ? up comparator sleep or standby mode v vbat ? 3 v v vbat ? 2.5 v v vbat ? 2 v v inhibit output (pin inh) vh drop high level voltage drop i inh = ? 180 a 50 200 800 mv i leak leakage current in sleep mode 0 ? 5.0 a t amb < 100 c 0 ? 1.0 a bus lines (pins canh and canl) v o(reces) (norm) recessive bus voltage v txd = v vcc ; no load, normal mode 2.0 2.5 3.0 v v o(reces) (stby) recessive bus voltage v txd = v vcc ; no load, standby mode ? 100 0 100 mv i o(reces) (canh) recessive output current at pin canh ? 35 v < v canh < +35 v; 0 v < v cc < 5.25 v ? 2.5 ? +2.5 ma i o(reces) (canl) recessive output current at pin canl ? 35 v < v canl < +35 v; 0 v < v vcc < 5.25 v ? 2.5 ? +2.5 ma v o(dom) (canh) dominant output voltage at pin canh v txd = 0 v 3.0 3.6 4.25 v v o(dom) (canl) dominant output voltage at pin canl v txd = 0 v 0. 5 1.4 1.75 v v o(dif) (bus_dom) differential bus output voltage (v canh ? v canl ) v txd = 0 v; dominant; 42.5 < r lt < 60 1.5 2.25 3.0 v v o(dif) (bus_rec) differential bus output voltage (v canh ? v canl ) v txd = v cc ; recessive; no load ? 120 0 +50 mv i o(sc) (canh) short ? circuit output current at pin canh v canh = 0 v; v txd = 0 v ? 45 ? 70 ? 120 ma ncv7341 http://onsemi.com 14 table 8. dc characteristics symbol unit max typ min conditions parameter bus lines (pins canh and canl) i o(sc) (canl) short ? circuit output current at pin canl v canl = 42 v; v txd = 0 v 45 70 120 ma v i(dif) (th) differential receiver threshold voltage (see figure 7) ? 12 v < v canl < +12 v ? 12 v < v canh < +12 v 0.5 0.7 0.9 v v ihcm(dif) (th) differential receiver threshold voltage for high common ? mode (see figure 7) ? 35 v < v canl < +35 v ? 35 v < v canh < +35 v 0.35 0.7 1.00 v v i(dif) (hys) differential receiver input voltage hysteresis (see figure 7) ? 35 v < v canl < +35 v ? 35v ncv7341 http://onsemi.com 16 v rxd v i(dif)(hys) high low 0.5 0.9 pc20040829.7 hysteresis figure 7. hysteresis of the receiver canh canl v split pc20060921.6 rxd txd 4 14 gnd 2 5 1 6 en 8 vcc 11 13 12 vbat inh vio +5v 37 10 9 wake 1k 10 nf 100 nf 47 f ncv7341 err stb r lt c lt +12v 60 100 pf generator 15 pf figure 8. test circuit for timing characteristics canh canl v split pc20060921.5 1nf ncv7341 rxd txd 4 14 gnd 2 5 1 6 en 8 vcc 11 13 12 vbat inh vio +5v 37 10 9 wake 1k 10 nf 100 nf 47 f 15 pf transient generator 1nf 10 nf err stb figure 9. test circuit for automotive transients ncv7341 http://onsemi.com 17 device ordering information part number description temperature range package type shipping ? NCV7341D20G hs can transceiver with bus error detection ? 40 c ? 125 c soic ? 14 (pb ? free) 55 tube / tray ncv7341d20r2g ? 40 c ? 125 c soic ? 14 (pb ? free) 3000 / tape & reel ncv7341d21g hs can transceiver ? 40 c ? 125 c soic ? 14 (pb ? free) 55 tube / tray ncv7341d21r2g ? 40 c ? 125 c soic ? 14 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. ncv7341 http://onsemi.com 18 soic 14 case 751ap ? 01 issue a on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncv7341/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative |
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